In the prior art, emitter coupled logic (ECL) has been used to implement clock divider circuits at high frequencies and, in particular, above 44 megahertz. The disadvantages of this prior art implementation are the very high power dissipation and the low reliability induced in the circuitry due to the high temperature operation. Also, these prior art ECL circuits at times had to incorporate many additional pieces of circuitry to compensate for time delays inherent in the decoding devices necessary to provide a specific dividing function. The increase in number of circuit components has added to the reliability problem.
The present invention accomplishes the divider operation by selecting specific binary count indications to be used in combination with the output of a J-K flip-flop such that the counter comprising a portion of the clock divider is preset (reset to a given count value) to again commence counting.
It is therefore an object of the present invention to reduce the number of parts and/or increase the speed of operation of a divider circuit while increasing circuit reliability.